In 1984, the Japanese Engineer Fujio Masuoka invented an electrical storage medium at the Toshiba Corporation. It would not require any energy to save data and could keep it for many years. The name was proposed by a coworker of Masuoka, Shoji Ariizumi, who saw the fast process of erasure for the first time and said that it reminded him of a camera’s flash. Nowadays, flash memory is everywhere. It is used as a solid-state drive in laptops or desktop PCs. It’s in our smartphones, in memory cards, thumb drives, and on and on. There exists a big variety when it comes to computer memory. They can be categorized as volatile and non-volatile storage mediums. Volatile Memories lose their data when electricity is turned off. Flash memory, however, is classified as non-volatile. It stores bits electrically and technically counts as an EEPROM or Electrically Erasable Programmable Read-Only Memory.

It means that data can be programmed into and erased easily from the device. For example, EPROMS can be programmed electrically too, but are not electrically erasable. They depend on UV light that must shine through a small window onto the die. In ROMs, data is written into the chip during manufacturing, whereas in PROMs data can be written into only once and through the help of a special programmer. The fundamental building block of conventional flash memory is the floating-gate MOSFET or flash cell. Floating-gate MOSFETS have a structure similar to one of normal MOSFETS, only difference being a floating-gate between the control gate and the substrate. This insulated extra gate has the key function to store electrons, thus enabling data storage. Source, drain, and the non-conductive silicon dioxide, all these parts are organized like in an NMOS. Let’s suppose the floating-gate MOS stores a logic “1”, which means that the cell is erased, and no electrons are trapped in the floating gate.

To read the data, we apply the shown voltages to the respective terminals, therefore creating a conducting channel between source and drain. In addition, a current sensor is used to measure the flowing current. The flow of electrons is then being interpreted as a logic “1”. On the other hand, a logic “0” is stored if electrons are trapped in the floating gate. Reading the data requires the same voltages as before. This time around, we will not measure a current because the trapped electrons have raised the threshold voltage of the flash cell. Therefore, only higher voltages at the control gate create a conductive channel. We now know how logic “1” and “0” are represented in a flash, but how about programming or erasing the flash cells? To program a logic “0”, a conducting channel is formed. The relatively high voltages cause electrons to increase their velocity horizontally. Also, electrons interact with the vertical electric field of the control gate, letting certain electrons tunnel through the gate oxide near the drain terminal.

as a result, trapping them in the floating gate. These electrons cannot escape from there for decades, saving data without the need for energy. Assume we now want to erase the content of the cell, so it holds a logic “1”. We apply the required voltages in order to push the right amount of electrons out of the floating gate into the substrate. The methods of programming and erasure have a destructive effect on the flash cell; thus, only a limited number of writing operations, also called program-erase cycles (P/E cycles), are possible. In order to increase the storage density of memory chips, the number of floating gates in a flash cell is increased. The discussed floating-gate MOSFET is a “single-level cell” and stores one bit of information. The “multi-level cell” stores two, the “triple-level cell” three, the “quad-level cell” four, and the “penta-level cell” five bits. All are placed on the same die; thus, more layers improve storage capacity while reducing cost per bit.

Electrons tunnel more often in a multi-level or triple-level structure and destroy the insulating oxide much faster than compared to SLCs, therefore reducing the number of P/E cycles as well as accuracy in the long term. Another difference is the reading speed. The more levels, the more time is spent to get to a specific bit. There are two types of Flash Memory available today: NOR flash and NAND flash. In both memory cells are arranged differently. In a NAND memory chip, all floating-gate MOSFETS are organized in a string and must conduct electricity to output a logic “0”. In a NOR flash, however, at least one memory cell must conduct in order to pull down the bit line, because they are connected in parallel to ground. NOR flash uses more space than NAND to save the same amount of information, since two flash cells share the same ground potential in this configuration. Therefore, NAND is cheaper. On the other hand, NOR memory needs less time to read a bit.

because of its direct access to individual cells. It also makes random-access possible, allowing NOR flash to be used for program storage, and NAND flash for systems with a need for high-capacity data storage. When looking at programming and erasure performance of both, it turns out that because of its smaller cost and space usage, NAND flash can justify being structured in pricier, smaller blocks, and smaller blocks mean less time is required to erase data. Talking about blocks, how are NAND or NOR flash generally arranged on a microchip? At first, pages. Pages are the smallest unit that can be programmed. In NAND flash, strings of memory cells make up pages. A certain number of pages makes up a block, and blocks are the smallest unit that can be erased. Blocks are organized into planes, which can perform read and write operations simultaneously. Usually, there are one or more planes on one die. The different numbers of pages, blocks, or planes vary from manufacturer to manufacturer. The die is then placed on a circuit board.

connected and encapsulated in a black plastic package. To achieve a higher memory capacity, flash devices hold multiple flash memory chips and a memory controller on their board. The memory controller is responsible for the communication between the flash chips and a computer, while also controlling read and write operations on a hardware level. Planar NAND flash has physical limits because memory cells are arranged horizontally. A new approach, called 3D NAND, however, uses cylindrical memory cells that are layered on top of each other, like a skyscraper does, for example. This makes it possible to build flash memory with significantly higher storage density, therefore reducing the price per bit even further. As of 2019, the highest transistor count in any IC chip is Samsung's 1 TB 3D NAND flash memory chip. It features over 2 trillion floating-gate MOSFETs with QLC technology (2.048.000.000.000). Semiconductor manufacturers will continue to break records, making possible cheaper and bigger flash memories, and that will make a lot of us happier!

Thank you for watching until the end and subscribe for more! [Music]

How Does Flash Memory Work? (SSD)

How Does Flash Memory Work? (SSD)