[Music] So welcome to this session. So we will be designing a compensated op-amp, okay? And first, we will learn the theory part, okay? Let me share this, okay, okay, yes. So basically our single stage op-amp, like uh, amplifier, we want an amplifier for our small signals, okay? So basically, this

is a okay normal amplifier. We all know, right? Yes, so we need to bias it properly so that we can work on small signals further, right? Yes, basically, there will be a V bias as well as a small signal V in, okay? So now what is the gain of the circuit?

We want to know this. This will be V out, like small signal gain, V out over V in, is nothing but minus let's say GM. GM of this and R, right? R. Yes, yes. So this is a small signal gain. And before that, we have to properly bias this MOSFET so that

we are giving VDD here and V bias here, okay? So this is the DC quantities, right? DC and VDD and, and why this circuit is not used because there is very, very, very much drawbacks in this circuit because for process, RD is varies, varies like significantly.

Okay, okay. So the gain is varying. So we are not getting a like a compact gain. Okay? So this circuit actually in practical, it is not used and the gain itself is very less, okay? For this circuit, okay, okay, okay. Now, so we are, and this is a

amplifier. This is not an op-amp, right? Basically, an amplifier means we are giving an input at one node and getting output from another node, but we know the op-amp is a three terminal device normally where we have two input terminals and one output terminal with again a, right? One is non-inverting

terminal and then is inverting, so our like single stage of P is, we all know this is called a differential pair with active load, right? Active current mirror load. Okay, so we are going to use an N pair with a P current mirror load. Okay, so this is our amplifier.

Right, so there are two input terminals, let's say VA and VB, right? And so for that we need which type of load, a current mirror, or an N current mirror? N. So which L you need? R. Okay, R. So actually for this type of circuit, we need a like

for the current, it flows from VDD to a node, right? A node. And for a current mirror, the current flows from a node to ground, right? A node to ground. So in this circuit, uh, which type of load we need? Which type of current? So we need from a

VDD to a node, right? For this amplifier. Okay, right? So we need a P current mirror. So this is a current mirror load. So this is also called a, uh, differential pair with active, active load, or active current mirror load. Okay, current mirror. Okay. And we need a biasing at the

tail. So this will be that, right? So this is called a, this is called a single stage of, and output is taken from here. Okay, so if, if I have any question in between, so can I ask in between? Yes, yes, always, always, always ask. Okay, so, uh, why we have this I

out, this, this is for biasing. Okay, nothing. This, this I out, uh, current source below. Yes, yes, this for biasing. Okay, so, so you can ask, there are two nodes, that is okay, that is VA and VB, and output is taken from here. Okay, right? So you can ask why the output is

not taken from there, let's say VX, why can you tell? Okay, I am I am telling basically if I take output from here, so we need a small signal G overall GM into overall R out, right? If I take out from there, so there is two paths, one path is there and

another path is there. Now, from looking upward, what is the uh are like the resistance of upward looking in impedance upward? So, this will be nothing but 1/gm4, right? G yes, so 1/gm4 is a very less impedance, right? Yes, so if I

take output from there, the gain will be very, very less, okay? So, that we are not taking output from there. Okay, okay, so this is a high impedance node, and if I take output from there, the gain will be very, very high, okay? So, this is why we have two terminals,

there, input terminal and output terminal here. Okay, okay. Now, now we have to determine what will be the like inverting terminal of this OPM and what will be the non-inverting terminal of the OPM? Can can you tell like what will be the like

VA will be positive terminal or negative terminal? Can can you say intuitively? I think VA will be the positive, VA will be the positive. Okay, how? Why this is the question? Why? Because maybe when when I think when VA increases uh I think then output will

also increase, increase. How how so? You you need to go to go through the signal FL right, actually you said right. So, let me uh let me tell how it is happening. So, if I increase this value now and let's say this is grounded right now, okay? Like

we are doing the superposition you can say Okay okay so now if this node is including so from here to there there is a 180° phase because there is a common source configuration of M2 right so that this voltage will decrease right yes then if this voltage decreases so this is

the same node so this voltage will also decrease right yes and then from here to there there is again a common source configuration of M3 so there is 180° phase so this voltage is decreasing so then this voltage will increase right so now increasing increasing this VA our output

is increasing and we know the V out of the op amp is nothing but gain times v+ minus V- right so now increasing let's say increasing this terminal so the output will increase right yes so that this is positive okay so VA is our positive terminal like non-inverting terminal and

VB is our inverting terminal okay so now again we can see that if this is grounded and there is an increment of VB then we can directly see that from here to there there is a common source configuration of M1 so if this voltage is increasing this voltage will decrease

okay so now if this voltage is increasing then the V out will decrease so this terminal is negative terminal okay yes so this is how we can comment on this so okay so this is okay so again let me draw the picture so this is a second stage

amplifier right single stage amplifier yes so we have the fixed topology right this is a differential pair amplifier right yes so this is our V positive this was our V negative so actually in practical life this this current source is not possible right directly we need to a

constant GM bias so we will discuss later and this topology will be looking like this okay so in our Cadence simulation we get the like better result okay like the practical result so this is how it happens the circuit okay so we need another current mirror at the tail node okay

okay this is our let's say I not itself and let's say this is one is to one right yes uh then these two are one is to one symmetrical and this these two are one is to one right these two are all symmetric these two are symmetrical like

M3 and M4 are symmetrical these two M3 and M4 M1 and M2 are symmetrical M1 and M2 are symmetrical and let's say for this case uh not necessarily this will be same but let's say here

let's say this is M10 okay and this is M so M10 and M are let's say symmetrical okay means means based on the I zero maybe we can change the sizing yes yes symmetrical let's say we need we need two i z here okay so the size will be

two here okay yes based on so this is the circuit and uh now so in like there is called a uh input common range okay like the the maximum voltage we can apply as bias here so this is called icmr okay so there is two range icmr plus and icmr

minus okay so the maximum voltage we can apply here so that all the transistors remain in saturation and the minimum voltage we can apply there so that all the transistors remain in saturation okay so we need to find this type of calculations okay like what will be the icmr plus and icmr

minus range okay okay okay so so how to calculate this so I am talking about things so actually if I increase this value now so if I increase this value which terminal is going going out of saturation F can we comment that yes which trans uh so let's say

okay go go go through the like go through the signal flow okay so if I increase this value now so this voltage will increase right yes because this is a common gen configuration of source for so this MOSFET is happy so this voltage is increasing so this MOSFET will go into

more saturation right this this m not so there is no problem now if I increase this value this voltage will decrease yes if this voltage is decrease so this voltage is decreased right so these two MOSFETs are like no problem like be in saturation right because this is the D

of the P MOS right yes like we are talking about the DC bias condition okay so these two are also happy but this like differential pair itself going to triode region because the then become decreasing right yes so these two MOSFETS are going out of the saturation and we

know that for the saturation VDS is greater than VDS minus VGS so this MOSFET is going to going out of saturation for so maximum limit is decided like the maximum is limited by this differential pair itself okay the maximum limit okay now so so what is the

maximum value we can like let's say V in Max DC DC okay in DC what will be that so we can see that to make the MOSFETs saturation we need a VD set of this M4 right M4 or M3 right yes so this will be

So okay, so so so this voltage is nothing but VDD minus VD set of four, okay, four or three. So this was symmetrical, we are assuming. So this is the V in max, okay? No, okay. So this is how we can calculate. So there are many techniques I will tell

you later how we can directly measure the maximum ICMR. So basically, this is the equation, okay, final equation, okay. So this V in max DC bias value maximum can be this VDD minus the VD set of this MOSFET, okay, okay. Now, what is the minimum

range? Uh, minimum we can calculate based on the below one. H yes. So minimum means now let's say we are decreasing the bias voltage, okay, okay. Let me so to keep, uh, yum, uh, this is decreasing, this will also be decreasing, so this MOSFET is going out of

saturation, yes, right? And this voltage is increasing, so there is no problem. But if this voltage is increasing, so there is a problem, uh, like so there is no problem because this is a DI connected. Now, so if the SG is greater than mod of, let's say

VTP, the MOSFET is always in saturation, right? Yes, yes. So there is no problem. So this M not MOSFET is going out of the saturation, so the minimum value of the V input is limited by the M not MOSFET, okay? Yes. So the V min you will find, so so we

need this MOSFET must be in saturation. This MOSFET must be in saturation, right? Yes. So if I do the calculation now, so you will get, uh, VN is nothing but VD set of M1, M1, sorry, one two plus VD set of let's

Say, I'm not so... this is the... not okay, and the VTn of one, okay? So this is the VT, so this is the minimum voltage we need to apply at this terminal so that all the MOSFETs remain in saturation. This is the theoretical portion, and when we are... we

we design in the Cadence, so we can see the this values, okay? And this will vary a lot, okay, across the PBT. Oh, this is the thing, okay? So you can, like, this is this type of equation you can write a KCL or KVL through this

uh, through this closed loop, you will get this type of thing, okay? So there is no issue, okay? Okay. So, so basically, this, this single-stage op-amp is also not, like, is not used so much because the gain is very, very less, okay? Like again, in, like, let's say for

TSMC on 18 nanometer, and for a, let's say, bias current of, let's say, 1 microamp or 2 microampere, the gain is limited by, let's say, 40, 40 dB, 40 dB means 100 in linear voltage by voltage. So basically, 

this circuit is also not so popular, okay, not so useful, okay? Yeah, for gain perspective. So we, we will go for the, go for, uh, like, let's say this is the output, go for second stage, right? CL. So we can see that this is a single-pole system, and

we are neglecting all the parasitics here and there, okay? So this is a single-pole system, so this is very much a table circuit, okay? Okay. I have one question here, if you want to, uh, increase the gain, what are the parameters in our hand to... so, so in

again we have GM right GM and out so this is the two parameter okay so for GM we need we need to burn more current there right and for our out we can use the Cascode structure so this is the two thing uh with with the same structure if

I want to increase means I need to change the W by ratio right no no no you don't need to change W by ratio we need to increase this current okay this tail current okay okay and we cannot burn the more current for a particular MOSFET for a let's say

let's say for TSMC and MOS 2 volt okay so this MOS will burn out okay in the so this is these are the limitations so now we will go for the further like we need to add further stage in Cascode right so this is called two stage op

okay so let me write that so let this structure is like that uh [Music] okay okay one thing so so we need to we need to the range of V out as well okay so I am not showing in this uh configuration I will be telling uh how

how the range of V out in DC uh changes for the two stage op okay okay now so we have this case so like how uh like DC uh DC swing limit yes DC DC output swing limit okay so I just want to know uh like how will

like uh what is like we forming the input and what will the looks like at the output no no no no so actually for output now so you need some limitations the output cannot be beyond some limit right because we need some biasing right so let's say our VDD is 1.8 volt now so

Your Vout cannot be more than 1.8 volts, right? Yes, and actually this is below, very very below than 1.8. So let's say it will be the Vout maximum maybe possible 1.5 volts, okay? So actually, we need to

find the expression for Vout. How much it can go, how low it can go? Okay, okay. So now, so we can use like this is the small signal output signal, right? So we can this signal to the N or P, but our normal, normally we are doing this, this

thing, okay? So we are going to give this to a PM, okay? And there is a h, so headroom here, we need a bias, right? Yes. So let's say we are biasing the same BGS like that, okay? Okay. So this was our final factor.

So this is the two-stage op-amp, okay? Current will be same in all three branches, right? No, no, no, no, no. Not necessarily. We can do anything as our requirement, okay? So let's say here is I not, 2I not, and here is 4I not. We can

do, okay, based on the sizing, okay? Okay, I, okay, okay. So, so let's say this is M6, this is M. We are directly taking that uh output voltage from first stage to here, here, huh? Yes, from there to there. So why we are doing that because this is not

affecting our loading, right? Because this is the high impedance node, right? So our voltage remains almost same, okay? Okay. So there is no loading effect, okay? No, I, uh, sorry, I didn't get like, no loading effect in the sense, what is called loading effect? You

studied loading loading effect huh so let's take we have a V out here constant V out of 1.2 volts okay from another branch from another block now if I kind of connect a resistance let's say R so what will the

voltage here it will remain 1.2 no because this let's say there is output impedance of R out right so the now the effective impedance from here like like uh modified to this okay so this voltage not like not remaining 1.2

it will like below 1.2 like let's say 0.9 volts or so on so this is called loading effect so if I connect this to a high impedance let's say R is infinite so so the 1.2 remain 1.2 yes

yes understood so so there will be paralleling resistance because of the so this is the infinite impedance part in theory so that there is no loading yes okay and loading effect is a very important term please try to understand okay loading very important term okay sure sure thank

you so now our like the our two stage op amp is designed and the gain for the previous case I have shown that so the gain can be around 80 degrees okay like 75 to 80 degrees okay now there is a problem okay why why because effectively there is a

resistance of this and this now so okay let me take the first second so what is the overall GM of the circuit this will be nothing but gm1 or 2 okay right and what is the R out of the circuit you know that right I am not

going to in like intuitive analysis it will take a lot of time okay okay so this means this is nothing but so for uh for uh small signal uh GM what do we do we short circuit the branch and find the small signal I out right yes and here

our V in is nothing but V in is nothing but V positive minus V negative small signal right so overall GM is nothing but small signal I out divided by let's say this V in okay V so V in is nothing but the positive small signal voltage

minus negative small signal voltage okay okay and we are also denote this like VD Okay small signal VD okay right and what is the r out here we all know so this will be nothing but R out of n parallel r out of T yes right

like the T r out and the M r out comes in parallel okay so basically uh looking from there the r out is this okay so this is the G gain of the CC so so so now what will be the final R out of the circuit like final uh GM of the circuit

now and what will be the r out of the circuit now now R out will be the like same like M6 parallel M7 so actually over for overall GM it is very difficult so what we will do we will we will make the two states separately okay so

actually this circuit if I write as OTA OTA means operational trans conductance amplifier okay so the circuit will be looking like this so this is called Ot Ot means the conductance okay trans conductance so this will be our gm1 or two and this

will be our GM so can you tell what will be the effective GM of the second block actually where our signal is going this is called the GM GM Block so gm6 okay okay okay so so I will be telling is dm6 okay yes okay now this will be let's say uh

minus plus and this will be minus and plus and there is a output impedance and there is a capacitance always there okay like which one like the routing or what this always be there means resist capacit after GM first stage still present there we are not

deliberately adding this type of thing so this model can be represent like this okay okay we are not adding anything right here we are not adding anything but actually they are present this type of things okay so let's say this is a G1 and this is C1 this is go2 and C2

Okay so this is this is the this is the GM Block positive and negative and this is the input terminal so this is out of the out of the box okay so this is the op okay okay this is this okay Okay g no no no no so can you tell what will

be the positive and negative terminal in this case let's say this is VA and VB so V out increases that V out also increases then this is increasing what will be the we also increases this first one are you sure are you sure are you

sure if this what about no not that we I'm asking after first stage no no I I want I want this now that is that is I'm going like signally that is increases then uh this VG uh vgs uh decreases so higher why bgs why you

tell me this from now on uh when VGS increases then after the first stage that V out increases right so then after the first stage this increases V out that this one yes yes and VGS increases this is a this is a P right so VGS decreases sorry VSG

decreases right because G why why why you are telling like that this is a 180° phase now and this is a common source amplifier so if this voltage increases this voltage has to decrease now so tell like that in that way okay okay so increase yes

yes like okay so this terminal becomes now negative and this becomes positive so I right in this way okay okay and you can find in like any standard books or any lectures okay okay this is how we can and actually uh this is basically not the thing so this

is like G so this is more generally this is one this is gm2 and here this is the small gm1 and this is small gm6 okay so they will add at output right I mean the final will be the adding of that is that's why 80 dB yes yes is 40

second is 40 we we do cascading for better gain so the gain is added now what is the DC gain of the circuit can we say or intuitively DC gain so GM Block means they takes a difference voltage and generates a current okay and the for a GM Block like

I am telling the basic thing GM is nothing but let's say plus minus VD okay and this is a GM so here I out is nothing but GM * VD okay this is the working of a conductance block transconductance okay so can we say what is the

DC gain of the circuit, and this G1 is nothing but the output conductance of this first stage, and go2 is the output conductance of the second stage. Okay, I am not writing as a resistance, okay, I am writing as conductance. And the uh G

on is nothing but one over, let's say, R1. Now, what is the D, so D of this two block will be nothing but this times this, this is right? Yes, in voltage by voltage from right. So, so the gain DC will be, let's say this is BD, okay. So, this will be

nothing but gm1 divided by G1 into the gain of this block, gm2 by go2. Okay, this is a D. Now, the question is what is the gm1 and G1? Okay, so we have already said that gm1 is nothing but gm12. G1 is nothing

but one over R out n of the first stage parallel R out P of the first stage, right? Okay, yes. And gm2 is nothing but gm6, and go2 is nothing but R out of 6 parallel R out of 7, one over

this, right? Yes, this is the thing. Now, this is seven, and this is six, so this is the... Okay, okay. Now, actually, okay, so this is the thing. Now, actually in this circuit, our phase margin is very, very less, okay, and and designing the value, these two poles uh comes

comes closer. Okay, so the, so our phase margin like decreases. Okay, so this circuit is also not used in our real circuit. Okay, so for compensation, for for like for the stability purpose, for stability purpose, for stability, we know the minimum phase margin we try to maintain is across full

P is 45 degrees right yes this is a minimum phase margin okay we try to maintain this and if these two poles come closer now so our phase margin decreases okay okay so that we can use a Miller compensation so what we do uh away Yes

actually we try to make a capacitor there so that this pole comes closer to the origin and this pole almost remains uh there if the gain of the second stage is like much more okay so this is called CC so basically these two poles are moving away okay let's say

previously the Bode plot was like this okay so these two are closer now so let's say this is P1 this is P2 now after doing the Miller the P1 moves towards the origin like that okay and let the P2 almost remain there okay like

that okay okay so and let's say this is the zero dB okay okay so let's say this is P2 now yeah so now let's say this is zero dB zero dB and previously let it was zero dB okay so zero

dB is a very critical point in our case our pole is on here and P2 let's say P2 there so this is called the UGB unity gain bandwidth right the gain is one in linear and in linear like one means in dB this will be zero right yes zero dB means one

in linear so so we can see that this is almost a single pole system right okay system why it is going to because of the we once we add the C that value decreased no the CC value here the effective CC value here is increased okay effective capacitance value at this

Note, so I will be telling you okay how this is happening. The main purpose is to, I want to split this two pole okay, split this two pole. So this is called the purpose of the Miller cap is to move the fast pole towards origin okay, so that our overall system behaves like a normal

single pole system and we all know the single pole system is always stable and for a perfect single pole system our phase margin is how much? 90 degrees okay. So 90 degrees is very very like good, like very stable circuit okay. So now what will be the

pole location? Can you say intuitively? Actually, we are not going to derive any mathematics, like it will be huge okay. So intuitively what, what is the like, now what is the effective capacitance here? Can you tell, uh, then? So this is the Miller cap

right, yes, and for Miller cap if there is a, so let me do that. So if we have a Miller cap like that and we have a negative gain circuit like that, CC and this can be represented as like that right? Yes, let's in and see out. Now what

OTA-01_Two stage op-amp design on cadence-01_ Miller's Compensation

Amit Bar

보상 연산 증폭기 설계 및 단일 스테이지 증폭기 한계 소개

이 세션에서는 이론적 개념부터 시작하여 보정 연산 증폭기 설계에 중점을 둡니다.

기본 증폭기 회로와 이득 계산(Vout/Vin = -GM*R)에 대해 설명합니다.

RD의 상당한 변화와 낮은 게인으로 인해 단순 증폭기가 비실용적인 이유에 대한 설명입니다.

단순 증폭기와 연산 증폭기(인버팅 및 비인버팅 단자가 있는 3단자 장치)의 차이점.

활성 부하가 있는 차동 쌍으로 단일 스테이지 연산 증폭기를 도입했습니다.

단일 스테이지 연산 증폭기 회로 및 출력 고려 사항 분석

앰프에 필요한 전류 미러 부하(P 전류 미러) 유형을 결정합니다.

미분 쌍의 꼬리 노드에서 편향에 대한 설명입니다.

임피던스가 낮고 이득이 감소하여 특정 노드(VX)에서 출력을 가져가지 않는 이유에 대해 논의합니다.

신호 흐름 분석을 기반으로 인버팅 및 비인버팅 단자(VA 및 VB)를 식별합니다.

상수 GM 바이어스를 사용하여 현재 소스를 구현할 때 고려해야 할 실용적인 사항입니다.

입력 공통 모드 범위(ICMR) 계산 및 제한 사항

입력 공통 모드 범위(ICMR)의 개념과 트랜지스터의 포화 상태를 유지하는 데 있어 그 중요성에 대해 소개합니다.

입력 전압을 높이면 트랜지스터에 어떤 영향을 미치는지 분석하고 최대 ICMR(ICMR+)을 결정합니다.

트랜지스터 포화도를 유지하기 위한 조건에 따라 최소 ICMR(ICMR-)을 계산합니다.

특히 고급 프로세스 노드에서 이득 측면에서 단일 스테이지 연산 증폭기의 한계가 있습니다.

2단계 연산 증폭기 설계 및 이득 향상

2단계 연산 증폭기 설계로 전환하여 게인을 개선합니다.

현재의 한계를 고려하여 GM과 Rout을 조작하여 이득을 증가시키는 방법에 대해 논의합니다.

2단 연산 증폭기의 DC 출력 스윙 한계 분석.

2단 연산 증폭기의 전류 분포와 높은 임피던스 노드로 인한 로딩 효과의 부재에 대한 설명입니다.

2단 연산 증폭기의 전체 게인 및 출력 임피던스 분석.

극 위치를 조작하여 안정성을 향상시키는 밀러 보정 기능을 도입했습니다.

충분한 위상 마진을 달성하기 위한 밀러 보상의 필요성에 대한 설명.

밀러 보상이 시스템을 보다 안정적인 단극 시스템으로 전환하는 방법에 대해 논의합니다.

밀러 보정으로 인한 입력 및 출력 커패시턴스 변화 분석.

밀러 보상이 극 위치(P1 및 P2)에 미치는 영향에 대한 추가 논의.

오른쪽 하프플레인 제로(RHPZ)와 안정성에 미치는 영향

오른쪽 하프플레인 제로(RHPZ)의 도입과 위상 마진에 미치는 부정적인 영향.

안정성을 보장하기 위한 폴 및 제로 배치의 설계 목표에 대한 설명입니다.

극과 0으로 인한 보데 플롯의 위상 변화를 분석합니다.

유니티 이득 대역폭(UGB)의 위치에 대한 논의.

위상 마진에 대한 RHPZ의 원치 않는 영향에 대한 설명입니다.

제로 캔슬레이션 기법 및 최종 회로 시뮬레이션

저항(RZ) 추가와 같이 RHPZ를 취소하거나 완화하는 기술을 소개합니다.

제로 캔슬레이션을 위한 저항 RZ의 계산 및 배치.

영점 위치에 대한 RZ 값의 영향과 새로운 극의 도입에 대해 논의합니다.

부품 값 및 전류 사양을 포함하여 시뮬레이션할 최종 회로에 대한 설명입니다.

회로에서 트랜지스터 M2와 M3의 대칭성에 대한 설명.

마무리 발언 및 케이던스 시뮬레이션 설정

책과 온라인 강의를 포함한 추가 학습 리소스를 제안합니다.

회로 시뮬레이션을 위해 Cadence에서 새 라이브러리를 설정하는 방법에 대한 안내입니다.

Cadence에서 새 회로도를 만드는 단계.

회로 설계를 위해 TSMC 65 라이브러리에서 MOSFET을 선택합니다.

OTA-01_Two stage op-amp design on cadence-01_ Miller's Compensation

OTA-01_Two stage op-amp design on cadence-01_ Miller's Compensation

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