First of all, they are talking about the fact that the equipment capacity of EUV has increased tenfold. Not only the equipment itself, but also the wafer production capacity has increased much more than the increase in EUV equipment. If we consider the EU wafer output as one, it has increased by 30 times. Even though the number of equipment has increased, the fact that it has increased by 30 times is a noteworthy point. It's not just about bringing in ASML equipment, but it's important that they have been able to achieve this level of productivity through their own efforts. The question is, can Intel do this right away? Hello, everyone. This is Professor Ahn from the School of Engineering. TSMC announced the next-generation node a while ago. Actually, it's been quite some time, and there have been many AI news during that time, so I couldn't update you. However, there are some things that I think you should know, so I will organize and share them with you in the future.

First of all, TSMC said they will introduce the 1.6nm technology in the second half of 2026. So, there is BS PDN, Backside Power Delivery Network. Intel plans to incorporate a technology called PowerVia into the 1.6nm technology, which is related to power delivery. If you search for engineering BS PDN, you will find it. I have summarized it, so please take a look. In fact, TSMC's method, known as Super Power Rail, is a bit different from Intel's method. I will organize a separate video for this. Apart from that, I talked about what TSMC will do in nanotechnology. Applying the NanoSheet structure, which is commonly known as GAA structure, to nanos is something we already knew. However, the main point I want to focus on today is that Intel is trying to quickly adopt and excel in the foundry competition by introducing it early.

It's a story that could break one's will. It would be declaring to go to 2 nanometers without introducing EUV. IBM has been using it continuously now. TSMC has been using 7 nanometers, 5 nanometers, and 3 nanometers continuously. Intel originally talked about ASM and quickly introducing High NA EUV, saying they will quickly adopt 14 homestrong. Even if they bring in ASML equipment, the issue won't be resolved. Even if they bring in next-generation equipment, Intel will inevitably fall short of TSMC. I will explain the reasons for this today. Firstly, the N2 process is a 2-nanometer process. As I mentioned earlier, they said they would introduce GAA transistors here. In the case of Samsung Foundry, they applied 3 nanometers, which they now call nanosheets.

Yes, before, there was a planar structure, the FinFET structure, right? Now, it hasn't reached down to 4 nanometers yet. Like this, with these fin-like fins, here is the core. Here, there is a source-drain area. So, in the gate part, the area on the surface is in two dimensions. It progresses like this in a fin pass, creating a three-dimensional structure. One, two, three, in a three-dimensional area, making it as wide as possible so that a lot of current can flow. Just like implementing it in a 3-nanometer process, when you actually look at the cell size, it's not a 3-nanometer size. In the past, the gate-to-gate pitch size was the standard, like talking about 10 nanometers, 14 nanometers. But at some point, if you compare the size itself, there is no correspondence to the 3-nanometer area in the configuration of these transistors. It just has the density of a 3-nanometer, but it doesn't correspond to an actual 3-nanometer size.

It was possible to make it much smaller. We are talking about that, and that was possible because it didn't protrude sharply here. Originally, it became flat as a planner. When it comes out sharply as a planner, it comes out through the surface. Now, if you make it with this nano-sheet structure, it will be bouncy. So, with this nano-sheet, like a sheet of paper, you can adjust it through the surface area like this. By allowing the current to flow through it, you can understand that it can transmit something much more solid and well. In the past, I made many videos about this, so please refer to them once. So, Samsung has already introduced 3-nano ES quickly, but in the case of TSMC, they said, No, we can continue from the 2-nano process.

If you understand it as applying the GAA structure, it was announced at the official CA event. Next, when you look at it again, it's now talking about 1.6 nanometers. This is called a16. Just like the processor name that was in Apple's iPhone, here, too, there is a16. Originally, we talked about N4, N3, and so on, like Nano 3, Nano 4, but now, looking at the Omstrong era, Omstrong 16, so it seems like they named it a16. However, in the case of Intel, rather than quickly switching to the current EUB, they announced that they would make 1.6 nanometers using what can be called the next high-n EU, not the current High-N EU equipment. I will explain what this means later. I will explain what this means later. Instead of the current High-N EU equipment, they announced that they would make 1.6 nanometers using the same equipment. What is the reason for this? Ultimately, it's because of money. Even if you try the High-N EU, the equipment itself is expensive, and even with the best optimization, it costs a lot and is really expensive. Originally, the EUB equipment was around 200 billion.

Now, as 30 trillion won has come up, it seems to be more than double, so Intel needs to adopt this quickly. Originally, at the Intel Vision event, they talked about starting the foundry and already made contracts with ASML and others by 2025. However, they said there is no need to rush that and mentioned TSC. They should quickly adopt it, so let's do it well. Even without that, we can make it well. After considering the cost issue, they decided that it is not so efficient. It's like not quickly adopting the GAA structure, like using the same tweezers as before, and just bringing in EU equipment as it is, saying that we can cover it sufficiently with our know-how. In fact, TSMC also brought in the EU equipment and announced how well they optimized it. I will tell you about this as well. Ultimately, Haeen's

Even without EUV, TSMC claims that it can achieve a very fine level by using a multi-patterning format 1.6 times or more. In the case of Intel, they are talking about using the '&' in the 1.4 or 14-strong process. This is also in 2026. So, if you look at the process history, the horizontal axis represents time and the vertical axis represents resolution in nanometers. In the past, there were times when it was at the level of several hundred nanometers. When EUV equipment came in, it was possible to reduce it to the level of 13.5nm with just one exposure. TSMC, on the other hand, claims that by still using EUV and doing multiple patterning several times, they can maintain a very small nano process level. They increased the number of gaps in the existing EUV lineup by 67%, so the number of gaps increases from 0.33 NA to 0.5.

As it grows, it's not just about increasing the number of new facilities. Many things have changed to increase the number of facilities. Equipment itself is expensive, and it is quite difficult to re-optimize based on this equipment. So the key is this. Through this yellow part, a wavelength of 13.5 nm is extreme ultraviolet. Before extreme ultraviolet, there was deep ultraviolet. So, deep ultraviolet transitions to extreme ultraviolet in a different pattern. The problem with this is that the wavelength is getting shorter. As the wavelength gets shorter, they contain more energy. Haven't we learned in the past that when the frequency of the wavelength increases, the energy increases accordingly?

You have to have a lot of it. Similarly, as the wavelength of light shortens, it carries a lot of energy, so work should be done in a vacuum state due to the characteristics of this extreme circuit. Because energy in the air is quickly absorbed or about 35 years, the resolution of a non-transmitting image continues to come in like this, eventually, this is it. It's a matter of how well you can focus the light. If the wavelength shortens, you can do it finely, but it's also important to adjust this focus according to the number of openings. Our camera is the same, right? If the camera's focus is not good now, it becomes blurry. The same goes for semiconductors. What we want to do in the current semiconductor process is to draw a picture on the semiconductor. If you want to draw a picture, you need to distinguish between the part that touches the beast and the part that doesn't. Once you focus on this, if it becomes blurry, it's not done properly.

There are some irregularities here, so the connections are not proper, leading to such problems. Therefore, factors like wavelength, process conditions, and the number of openings are all important. By reducing the wavelength or increasing the number of openings, a much smaller circuit pattern can be implemented. This is why, for the reasons mentioned, the height of the high NA is finely adjusted to 0.33 or 0.5. However, if the wavelength decreases, as I mentioned earlier, it needs to be well maintained in a vacuum to ensure proper focus. Therefore, it is essential to consider these factors carefully. What you are currently seeing is likely the ASML EU equipment, which is the next version of the EU system, the EXE 5000, first introduced in early 2024. It seems like Intel has taken this equipment, and thus, the number of openings will change. Ultimately, the number of openings determines how well the light is precisely directed and focused.

Well, simply put, as the number increases, it plays a role in gathering light. It shows the role of gathering the spread out things finely towards that side. So, to achieve this high aperture ratio, you need to use a larger lens. Therefore, if you use a lens with a slightly larger diameter or a shorter focal length, you can gather light better when focusing on a wider area. That's why companies like Intel are saying that they will introduce a node every four years and are talking about 18 nanometers. They have already entered the research phase for high-end. They haven't done anything with it yet, they just entered the research phase first. Anyway, Intel introduced high-end UVB before even 14nm Tron, which could change the game. Because the boundaries are too narrow now.

There are parts that are converging on TSMC, so there are benefits from the competition among competitors, and ultimately, the beneficiaries will be the customers. As you can see in TSMC's current roadmap, based on 2024, they are now coming out with the N32 node, and various products are currently being released. Qualcomm is also coming out now, and Apple's products are also expressed as N3 1 to 3-nanometer process, which is N3E. Originally, it was called N3B or N3A. The process was applied by Apple in the first generation of 3-nanometer, and now it uses EUV equipment 25 times in the process. The more EUV process is used, the longer it takes and the more complex it becomes. In the case of N3E, it uses 19 times of immersion lithography equipment to adjust the price a bit lower. So, there is an expectation that the yield will be better.

It's about getting cheaper, but if you look at 2025, there will be N2 processes, and now they will apply the Gater Round here, and then continuously new N3 processes will keep coming out. Performance X and so on have been coming out, but now they are looking at applying BS PDN when they reach 166A. And since the foundry prices keep getting more expensive, TSMC is talking about continuously creating derivative processes like 5 nanos, 4 nanos, 3 nanos, and so on, utilizing the existing ones very well, making cheaper nodes. For example, making cheaper things like M4C processes from the nano node. It will become a cost-effective version. So, simply applying BS PDN quickly or applying Gate-All-Round quickly or doing Hynix UVI quickly, we will quickly release them.

There are parts that cannot be solved on their own. To explain these parts, first, if we follow the introduction of EUV, when it is introduced, it becomes expensive. So, the yield has to be good. As I mentioned earlier, in the case of N3E, there are 19 stages of EUB process, which results in better yield compared to the previous 25 stages of N3B process. What does this mean? Since less EU equipment is used, the yield is better. When the yield is good, it means that the price can be lower. Ultimately, there are a certain number of wafers per equipment. More wafers need to be produced faster, with good yield. Sufficient equipment needs to be utilized. However, if we introduce high-end EUV, it comes at a higher cost, making it difficult to catch up with the yield. In the end, it becomes economically unviable.

So, TSMC and EUV will not be used now. Just using ArF is enough because we have done a lot with ArF. Basically, if we introduce EUV, we need to optimize the process. So, not only lithography equipment but also various tasks such as photoresist, etching, deposition, and so on need to be optimized according to the new reasons for introducing EUV. It is better to use existing know-how for optimization. Moreover, now with multi-patterning or cell libraries, there are ways to calculate power efficiency properly. TSMC has been continuing these aspects. To explain this in more detail, this is actually the content that TSMC presented here.

What you are watching is a discussion about EUV. They talked about 2019 and 2013. First of all, they are saying that the EUV equipment itself has increased tenfold. Not only the equipment itself, but also the wafer production has increased much more than the increase in EUV equipment. If you compare the output of EUV wafers to before, it has increased by 30 times. Even though the equipment has increased by 10 times, the output has increased by 30 times. This is a remarkable point to pay attention to. It's not just about bringing in ASML EUV, but it's important that they have achieved this level of productivity through their own efforts. Can Intel do this right away? And not only that, they significantly improved the lifetimes of things like EUV pellicles, extending their lifetimes by four times.

Increasing this means that we have more time to rotate it, so we can produce wafers better, and it is said that the coupling ratio has been reduced by as much as 80 times. So, to protect the pellicle with an EUV mask, we need to attach it precisely. It needs to transmit well, so it needs to protect the mask while transmitting well. Even if it is said that it transmits 90%, it needs to pass twice, and it's also TSMC's know-how. Looking at how much of this EU equipment they have, TSMC has always overwhelmingly secured a lot. Intel, on the other hand, hasn't had much. Intel could have used internal capacity for manufacturing, and they also entered the foundry business late, but they still lack EUV equipment. The current trend is fanless, so NVIDIA, AMD, Qualcomm.

Companies that only design these kinds of chips, companies that just create designs, when they entrust TSMC to make the chips, in the current situation where they are trying not to spend a lot of money on expensive N3 processes, TSMC, which has strong expertise, can make much more profit and have the possibility to produce while earning a lot of money. From this perspective, there may be some risks in whether Intel, a latecomer, will make a proper business by quickly introducing high-end EUV. However, Intel continues to receive subsidies from the United States and is doing something, even if the money doesn't come in immediately, just like China supports its domestic companies, the U.S. is also actively supporting Intel. So, even if there is an immediate loss, in that sense, there is time to continue building competitiveness.

There may be parts where you can see that, right? So today, let's talk about why TSMC is so far ahead these days. Recently, TSMC talked about their advanced process roadmap. Not only that, in fact, related to EVs, even if you have all the EUV equipment, we are doing so well like this. We are even confident to say that we will use it in our process. The reasons for being able to talk like this confidently are the parts where this confidence is revealed. On the other hand, for companies like Intel, in order to quickly accumulate this know-how, they need to continue making chips, optimizing the process, and trying out these aspects a lot. Not only that, in the future, when the era of nanos and EUV comes, BS PDN, so in the case of Intel, they use a power via, while TSMC uses a power lead method. These are different methods, and I will explain this in more detail later. This way, TSMC is overwhelmingly ahead.

Amidst the ongoing fierce competition in the monopoly structure of the foundry, An Dae-gong was determined to continue following to see what extraordinary moves Intel's heavyweight singer would show next.

tsmc, 차세대 노광장비 ‘없이’ 1.6nm간다...? 인텔이 High NA EUV를 도입하더라도 tsmc가 강력한 이유

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tsmc, 차세대 노광장비 ‘없이’ 1.6nm간다...? 인텔이 High NA EUV를 도입하더라도 tsmc가 강력한 이유

tsmc, 차세대 노광장비 ‘없이’ 1.6nm간다...? 인텔이 High NA EUV를 도입하더라도 tsmc가 강력한 이유

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