hi everyone welcome to vlsi academy today we will understand about a very important phenomena which is especially important from the interview perspective at least because it tests a fundamental knowledge about manufacturing which of chip that is cmos latch up issue this phenomena occurs inside the standard cell so we will understand it from that perspective only so in this c mass this is our n well and this is our p substrate and we have seen this layout already in one of the previous videos this is your diffusion region so this is your p plus this is also p plus and this is your n plus and this is your n plus so like this and then this will be your drain connection this will be your gate terminal this should be your source similarly here also this should be your drain gate and source connections so in this layout what actually we have done is these are the two gate terminals in which your input will be connected so this is your input connection and there will be one output connection here so this is the connection that we have done and this

one is your annual diffused region. That is your pmos with the base p substrate. We have nmos here. So that is why it is a complementary mass, which has both. And we have connected it such that we have pnp here and npn outside. So these are the junctions that we have created on our own. But what happens is we will, while working of this transistor, what happens is there are some parasitic elements that can be diodes or transistors that gets formed inside the chip. Now the question is what is parasitic element. So parasitic element is something which we have not constructed. It is getting formed on its own. And it is an unwanted thing which does not is needed and is causing the problem to us. Let us try to understand the latch up problem here. So we will take two transistors for modeling the latch up issue. And these will be npn and pnp transistors that would be formed inside the cmos. And we need to understand how actually that would

happen so in this pnp this base is your n well, and let us say that we have an n plus region which will be actually connected to your vdd, and your drain is also connected to vdd so this will your vdd line, and similarly we will have one p plus region here also and that is for modeling, and it will be connected to vss so this vss, and this our source also will be connected like this, and what happens is so your this n plus will be connected which will represent some resistance, and will be connected to the base of this pnp so this uh the resistance will be represented by the well resistance that will be calling as arvel, and similarly this substrate will also be connected to the base so in this case this will be your base, and it will also be connected via some resistance, and it will be connected to the base so this resistance will be your substrate resistance, so these two transistors that is your this pnp, and this is our npn.

and these two transistors are here only for modeling purpose. We are just trying to model what happens inside the transistor during the operation. So let's say if it is operating and for some reason if there is any voltage shoot at the vdd terminal or undershoot. So let's say first overshoot. In the overshoot case, what will happen is this terminal will be connected to the vdd and this p plus reason. This is connected to your emitter and this, this collector terminal will be actually connected to the base of your other transistors. So basically it will be connected like this and it will be connected like this and this n plus will be connected like this. And we are trying to understand what will happen in the case of overshoot. So if you see this drain and source terminal of your pmos, they are connected to the emitter, the emitter portion of the transistor of pnp. These are connected by drain source of pmos. Similarly, drain source and gate terminals of nmos, they are connected to the emitter.

so this is your emitter. This is your collector. Collector is fed back to the base, and this emitter is connected to the n plus, or you can say source and drain, and gate terminal of the npn transistor, which is a parasitic transistor. Now, if you see, we have a direct path from vdd to ground. We have a direct path through the parasitic elements from vdd to ground. During the operation, it can go like this, but we have these uh parasitic elements reverse biased, so that is why current does not flow through this path. Ideally, input or output should be at vdd, but let's say if your output or input is greater than vdd, at that time, your p plus region will be more positive, and that will create a forward bias region in this pnp, and this emitter will be more positive than this, and that is why current can flow from emitter to base, and like this, it will turn on this pmos will turn on, and that case, hence, if input or output is greater than vdd, in that case, your veb this region you can

say veb region emitter base region will become forward bias if that becomes forward bias then your pmos is turning on or you can write pnp that pnp transistor actually this pmos is not correct term because we are modeling it through the bjt transistor so pnp region is your turning on it will turn on in that case then current will flow from collector to base of the npn transistor and your base emitter junction of your npn will also becomes forward biased and once it is forward biased then your npn will be also turned on and then we will have a complete path from vdd to ground from this area if you see then pnp and npn are connected like this so that is why we will have a path of current from vdd to ground this will result in a power ground shot and can result in a complete failure of this standard cell or it could be complete failure of chip also now let us consider the second case where you are saying that input or output is lesser than ground if the

input or output is lesser than ground, then basically this base voltage is at substrate voltage, and we are saying that this n region is more negative than what the voltage is of substrate. So in the case of npn, if we say what happens is your substrate voltage is your source voltages are negative, and substrate is at higher potential. So that is why your base emitter voltage is forward biased, and hence your npn will turn on, and your npn gets turned on. Once this transistor is turning on, there is collector base feedback, and collector current will flow from here to the base, and that is why this pnp also gets turns on, and hence once again we have current from direct ground to vdd path we have, which will result in a vdd ground shot or power ground shot, which will result in a failure of the chip again. So in both the cases if you have input or output greater than vdd or input or output greater than lesser than vss, you can say voltage overshoot or undershoot on the input or output that could be because of

any external factors like noise. So, because of those fin those factors, you can turn this factor, this phenomena on. Now, the next question that could be asked in the interview is why this phenomena is called as cmos latch up. So, if you see the phenomena of getting the short circuit from vdd to ground is occurring because of input or output disturbances and this collector is feeding back to the base of this npnp and this collector of pnp is feeding back to the base of npn and this feedback loop is formed here. Now, even if you remove these disturbances which was causing this issue, it can still sustain on its own and current will once this has turned on the current will keep feeding from vdd to ground and even if you have removed this input or output disturbances it does not matter now because this feedback is self-sustained now and that is why this is a latch up. We hope we have conveyed the concept of cmos latch up properly. If you have any questions or doubt you can

ask in the comment section. That is all for this video. We will come up with more concepts in further videos. Please do like, share, and subscribe to the channel. Thank you.

PD Lec 39 - CMOS Latch Up | VLSI | Physical Design

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PD Lec 39 - CMOS Latch Up | VLSI | Physical Design

PD Lec 39 - CMOS Latch Up | VLSI | Physical Design

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