In this video, we are going to look at a brief history of the semiconductor packaging industry. Packaging refers to the integrated circuit's carrier and enclosure. It protects the silicon die inside from physical damage, while also allowing it to be connected to other devices. The industry has long been chopped liver, overshadowed by the sexier work of wafer fabrication. But it's important and we should know about it. Let’s go. What is Packaging? ICs are precious little snowflakes. They need protection from the real world, which is full of damaging influences. Particles can get in and interfere with operations. Moisture in the air can cause their metals to corrode. High temperatures generated during operations can cause the IC to degrade or even fail outright. Vibrations or jolts can damage the chip's capabilities. And so on. The packaging is for protecting from all of these

threats. Let’s talk about what is 
inside. First, we have your die. The die attaches to a metal 
support called a leadframe, oftentimes through the use of 
clips, adhesive, or straps. The leadframe has wires attached to it which connect it to the outside world. 
These are called “bond wires”. And then finally there is a plastic or ceramic or metal enclosure surrounding the die, 
the leadframe, and the bond wires. This whole setup is considered by the industry as 
only the First Level of semiconductor packaging. The second level refers to the circuit board. The third and final level refers to the system's 
final enclosure, like the desktop PC's chassis. Back End The process of encasing the 
fabricated die into its Level 1 package is referred to as the Back End. We can further break down Back End processes 
to two major steps - Assembly and Test. Processes differ based on the technology, 
but here is the vanilla workflow.

In Assembly, we start by cutting the dies out of the completed wafer and inspecting them. After this, we have to put the dies onto the package's leadframe - called Die Attach or Die Bonding or Die Mounting. Then we attach the very small bond wires to the dies, which allow the chip to communicate with the outside world. This step is called wire bonding and was pioneered by Bell Labs in the 1950s. After that, we put the die into its ceramic or plastic package to protect it from the outside world. At the start, this process had to be done manually, making it one of the first things to be outsourced abroad. Since then, machines have taken over and a swath of new bonding techniques have been introduced. Discussing them is beyond the scope of this video, but you should know they exist. ## Beginnings

Throughout its history, packaging's goals have stayed rather consistent: Help the IC achieve its full functionality and don't get in its way. Be as small as possible. Be as cost effective as possible. In the beginning, only military or aerospace companies used semiconductors. Price was less of a concern than total reliability. Ergo, most semiconductor manufacturers packaged their dies in hermetically-sealed cans made out of ceramic or steel. This prevented any contaminants from messing with the chip, but there were serious drawbacks. Ceramics and metal cost a lot. They were also heavy, which meant that the circuit boards they were attached to had to support all that weight. This made them heavy too. Fairchild Packaging took a big leap forward with - who else? - Fairchild Semiconductor. When Fairchild started producing their revolutionary planar ICs in the late 1950s,

they packed them in the same TO-5 and flatpack packages they used for transistors, just with a few more leads. We will talk about flatpacks a little later in this video. First, let us talk about the TO-5. The TO stands for Transistor Outline. A TO-5 kind of looks like a squid - basically a metal can and metal lid. Fairchild's first Micrologic chips were accordingly etched in a round shape. But the TO-5s' awkward round shape made it difficult to attach onto and arrange on a board - adding to the labor cost. Worse yet, TO-5s limited how much data the chip can take in and push out. They maxed out at just 8-10 pins. Fairchild's new logic circuits needed far more than that. TO-5 packaging diluted the IC's advantages and worsened its disadvantages. With this situation,

how were ICs ever going to get to price parity with germanium devices and vacuum tubes? Plastic Encapsulation. In response, Fairchild developed 2 new packaging techniques. The first was plastic encapsulation. It sounds fancy, but the way they did it back then was to put the IC die on a ceramic bead and cover the whole thing with a plastic blob. This method had some issues. Plastic can be permeable to certain chemicals, leading to concerns surrounding contamination. And plastic can shrink or grow depending on outside conditions like heat - inflicting mechanical stress on the chips inside. However, plopping plastic onto a chip required very little skill. This meant that Fairchild could outsource its assembly work to cheap manual labor in Hong Kong or South Korea - one of the first such electronics companies to do so. DIP. Fairchild's second idea would forever change semiconductor packaging. Fairchild's digital systems laboratory head Rex Rice created a new lead configuration

for an IC. The leads were spaced about 100 
thousandths of an inch (2.54 mm) apart - the industry term for this measurement is lead 
pitch - and came out in a single line. You would attach the package to the circuit board 
using what is called through-hole mounting. Here, you insert the package's leads 
through literal holes drilled into the boards. The holes have large, round 
solder-contact areas surrounding them. After insertion, you solder 
the leads on the backside to secure them. The method for doing 
this was called wave-soldering. Tests found that this new in-line packaging 
system fit all the criteria. It can accommodate more IO - some 12-16 pins at the start. 
It simplified the circuit board layout. And finally, it took less time and skill 
to assemble. The in-line arrangement was far simpler than the TO-5 
can's circle-shaped leads.

Before deploying the product, Fairchild first consulted with customers and end-users, who did not like the single line arrangement. However, they would be okay with two lines. So Fairchild revised the prototype to two rows of in-line pins: Dual Inline Packaging or DIP.

## Fall of the DIP Introduced in 1965, the simplicity of Dual Inline Packaging cut the costs of assembly by a factor of four. The industry widely adopted it throughout the 1970s and 80s. During those twenty years, DIPs - which include ceramic and plastic versions - held some 80-90% market share when measured by value. However, as the industry moved into the 1970s and the era of Very Large Scale Integration or VLSI, demands for IO density kept growing. Some VLSI chips would require as many as 300 leads. More leads forced the DIPs to grow increasingly large. DIPs can have

64 or even more leads, but doing so gave 
them impractically large board footprints. If trends continued the way they were, the DIP packages would end up being 
far larger than the dies themselves. This invalidates the various miniaturization 
gains in semiconductor manufacturing. Packaging's 2nd Revolution. In response to this trend, a series of 
new packages capable of accommodating far more leads emerged. The packaging 
industry's second big revolution. This generation of packages 
was defined not by their shape, but rather how they were attached to the circuit 
board. Surface-mounting technology describes a style of mounting packages onto the board using 
flat patches of solder already on the board. Surface-mounting had several advantages 
over through-hole mounting. First, because through-hole mounting required you to solder 
the back side of the boards to secure the DIPs, you can only use one side of the board. 
With surface-mounting, you can use both.

This alone increases the theoretical number 
of packages on a single board by 35-60%. Second, it allowed us to move the leads closer 
together, or in other words, for a smaller lead pitch. This is because you no longer have 
the solder contact areas around the holes. And third, you can use cheaper boards. 
Drilling a hole into a board costs money, and there can be up to a 1,000 
holes on a standard board. Contemporary estimates found that a surface-mount board costs 13 cents per square inch, while an 
insertion-hole mounting board costs 15 cents. Furthermore, the boards aren't peppered with 
holes anymore, which means they don't need so many layers to maintain their structural 
integrity. Another cost-saving measure. Previously, all that the surface-mounting 
had to be done by hand, which - considering the smaller lead pitches - required a 
great deal of skill and training. This

was the primary reason why surface 
mounting didn't take off at first. New automatic machines finally closed the loop on 
this. Manufacturers now use convection heating - hot gas or even infrared heat rays - to solder 
the packages onto the boards. Basically, ovens. The Rise of Surface Mounting The origins of modern Surface-mounting 
technology are murky, and there isn’t one significant inventor or eureka moment. I mean, the concept of attaching stuff to 
a board is not exactly ground-breaking. The earliest credible mention is a British 
patent filed in 1960. It describes resistors, coils, and such attached to a printed board using an adhesive. The connectors 
were connected using solder. Early adopters in the 1960s 
included the US military, which used flatpacks for their missile 
guidance computers. The flatpack was a stackable rectangular glass and ceramic 
package that was surface-mounted onto a board.

The flatpack was invented in 1962 
by Yung Tao of Texas Instruments. So actually a few years older than 
the venerable DIP. I couldn't find much more about inventor Yung Tao 
or his life, which is unfortunate. In the late 1960s, the Swiss watch 
industry adopted surface mounting as a way to reduce the number of 
electronics in their watches. They popularized what is called the 
Small-Outline Integrated Circuit, sometimes also known as the Swiss Outline. The Small-Outline looks like the DIP and is made 
from the same molded plastic materials. However, it is far smaller - a third as high 
and half as long. This was because its 28 gull-wing leads are spaced 
far closer together. Possible again, because we are directly 
mounting these onto the board. They are called gull-wing leads because their 
shape is somewhat reminiscent of seagulls' wings.

Seagulls are birds that steal your hot dogs at the beach. In the 1970s, the Japanese electronics industry began adopting surface-mounting technology for their car radios, TV tuners, and TV cameras. It is likely they got the idea from Europe - Germany or Britain, perhaps. By the 1978-1980 period, the semiconductor packaging industry had started moving towards surface-mounting - with numerous published articles discussing its use for increasing packing density.

## SMT Packages

In the early 1980s, the Japanese revived the old US military flatpack to create an updated, surface-mount compatible version called the Quad Flat Package or QFP. With the Quad Flat, we have the leads projecting down and away from all four sides of the square package. Depending on their size, the Quad Flat can offer anywhere from 20 to 240 leads. Pitches shrank to as small as 1 or 0.65 millimeters. You can go guess how many inches that is.

The Quad Flat quickly evolved, pushed along by consumer demands for smaller and smaller consumer electronics. The Japanese industries introduced yet smaller packages like the Shrink Quad Flat Package, the Very Small Quad Flat Package, and the Thin Quad Flat Package. Pins and Balls. On the other end of the spectrum, new structures outpaced the Quad Flat on the lead count front. People realized that having the leads come out of the sides meant that you couldn't use the real estate underneath the package itself. So for high lead-count devices, the packaging industry revived an old IBM invention - the Pin Grid Array or the PGA. First introduced in 1971, the square-shaped Pin Grid Array can handle hundreds of leads on its underside. IBM invented the Pin Grid Array for high I/O uses in the computer industry. Those packages were made from ceramic, which not only made them more expensive, but also their circuit boards since those boards had to

get thicker to handle the added weight.
Plastic variants were later introduced. Pin Grid Arrays were invented before 
the surface-mount revolution. So a surface-mount compatible cousin emerged 
in the 1980s - the Ball Grid Array. With these, solder balls are used rather than 
pins to connect the chip to the circuit board. One big disadvantage of the 
Ball Grid was that you could not easily visually inspect the solder 
connections underneath the package. X-ray and electrical tests are often used instead, with badly soldered packages 
removed, re-balled, and re-applied. Solder ball technology appear in another packaging 
innovation that popularized at about the same time as the BGA - flip chip. This is where the silicon die is flipped so that 
it faces downwards. To build the interconnects, we ditch wire bonding entirely and connect 
using bumps and balls on the chips' pads. Flip chip technology is still used today 
and offers several benefits. First,

there is more contact with a heat sink, 
which dissipates more heat. Second, electrical signals have a shorter distance 
with flip-chip interconnects than bond wires. Smaller and Smaller. Starting in the 1990s, consumers 
started buying smaller electronics like mobile phones. Smaller devices 
mean smaller components, chips, and packages. Space became 
a premium in a chip package. The industry measures this using what 
is called Packaging Efficiency - the ratio of the area occupied by 
the active device, the die. In response to this, the packaging 
industry developed the Chip Scale Package, which entered the market in the mid-1990s. Chip Scale Packaging is an evolution of the 
aforementioned Ball Grid Array and refers to any package where the bare die occupies 
80% or more of the total package area. Taiwanese OSAT vendors like ASE Group rose up 
on the back of such ultra-compact packages.

One prominent implementation of this concept is called wafer-level packaging. This is where we hook up all the die interconnects before we cut those dies out of the wafer. It's not only very cost-effective, but gives you very small packages.

Advanced Packaging As I mentioned earlier, the advent of Surface-Mounting Technology created a new generation of packages and techniques. As Moore's Law slows down, packaging technologies have seen yet another surge of investment - creating what we can call advanced packaging solutions. These new packaging technologies now have a much more direct role to play in the system's overall performance. SemiAnalysis has a fantastic multi-part breakdown on advanced packaging that I think drops the mic on the subject. Perhaps the most well known of these are chiplets. This is a variant of what are called Multi-chip Modules, or Hybrid Circuits, or System-in-Packages.

I did a video about it previously. Most prominently, AMD used them to create a disruptively great product. Going 3D. One special area of the multi-chip world involves 2.5D and 3D integration. These are especially cool. 2.5D integration is where we put multiple dies side-by-side on top of an interconnect substrate called a silicon interposer. This silicon interposer doesn't have any logic but is just made up of many embedded interconnects. There are a few consumer products using 2.5D integration today. For instance, AMD's Radeon R9 Fury GPU, first introduced in 2015. As the name implies, 2.5D is an intermediate step towards 3D packaging - stacking and connecting multiple dies. We are now able to use a whole new dimension to achieve packaging efficiencies of over 100%. Connecting these dies may require something more heavy than your standard

wire bonds - bringing forth new concepts, like the Through-Silicon Vias or TSVs. I am working on a future video on 3D integration and Die-Stacking. So keep an eye out for that ... if I ever finish it. Conclusion: The semiconductor packaging industry is truly a chaotic one. There are so many different technology trees growing concurrently with one another. Each branch developing and splitting for a certain significant need. New technologies are built on top of those, addressing particular niche applications. And then suddenly before you know it, you have no idea why this new thing - which you saw fail a long time ago - is now such a big deal all over again. In the semiconductor packaging world, ideas are created and then vanish off the mainline ... only to return to the forefront when their time is right. Love it. Expect more deep dives into semiconductor packaging in the near future as we familiarize ourselves with this new world.

A Brief History of Semiconductor Packaging

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A Brief History of Semiconductor Packaging

A Brief History of Semiconductor Packaging

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